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The shift to chiplets is one way companies are working through this problem — but chiplets still have to be connected together in a common socket standard. AMD laid the groundwork for its modular chiplet approach back with first-generation Ryzen. One major challenge for AMD is maintaining pinout compatibility while shifting from a monolithic four-core die built on 28nm to a mixed-core plan with 14nm and 7nm silicon deployed on the same package.
Enhancements and improvements to the socket can be made, but changing the socket design breaks backward compatibility. AMD lowered its bump pitch from um to um for 7nm Ryzen, despite the challenges of doing so.
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There are only two vendors building these kinds of solutions at the moment. In order to make the shift effectively, AMD had to transition away from traditional lead-free solder bumps and adopt what are known as copper pillars, with a lead-free solder cap.
This allows for markedly smaller bump pitches. New materials and interfaces were also required for PCI Express 4.
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The routing diagram for the underlying chip. The four rectangular blocks in each CCX likely correspond to the L3 cache. These improvements are the first phase for chiplets and chiplet designs.
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